Integrated circuit switches used in integrated circuits can be formed from solid state structures (e.g., transistors) micro electro mechanical systems (MEMS), formed from passive wires inside a hermetically sealed cavity. Other devices formed inside a cavity include bulk acoustic wave filters (BAW filters) or resonators (BAR), or motion detectors and accelerometers. One such example is cellular telephone chips containing a power amplifier (PA) and circuitry tuned for each broadcast mode. Integrated switches on the chip would connect the PA to the appropriate circuitry so that one PA per mode is not required.
For illustrative purposes MEMS switch devices are discussed herein, although the discussion applies to any device formed inside a cavity. MEMS structures can come in many different forms, which are fabricated using many different processes, including chemical mechanical planarization (CMP) processes. In general, many of the methodologies, i.e., technologies, employed to manufacture MEMS have been adopted from integrated circuit (IC) technology. In particular, the fabrication of MEMS uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, the CMP processes can be used to planarize materials, e.g., materials comprising the MEMS beam. However, CMP steps can result in underpolish or overpolish, raising fabrication issues. As an example, underpolish causes the MEMS capacitor to short or results in MEMS cavity voids; whereas, overpolish causes MEMS cavity heights being out of specification. In addition, it is known that lithography depth of focus issues can arise due to taller cavity structures, for example. Other problems include reactive ion etch (RIE) rate or bias variability, induced by the local layout or pattern factor of the chip.
Metrology structures assist in the fabrication of the devices on the chip. These metrology structures can also be used as a means to measure focal planes for performing more accurate lithographic and etching processes, amongst other features. The metrology structures can also be used to test the electrical characteristics of the MEMS structures fabricated within a product chip. The metrology structures are fabricated within the dicing channel, which is referred to as a kerf, or randomly placed within a test die. However, it is difficult or impossible to place a MEMS test structure within the kerf, due to size limitations. For example, the MEMS test structure can be about 200 microns in width, while the kerf is typically about 40 to 90 microns in width. Also, it is known that metrology structures randomly placed within a test die or within the kerf can affect the actual devices in the chip product due to, for example, proximity effects and metal pattern factor effects.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.